To enable the student to analyse and design digital circuits using state machine and othertechniques. To implement digital designs using Flip flops and combinational logic. To assessand evaluate real world effects like setup and hold time issues, signal reflections andrelevant real world issues.
Boolean Switching Theory and Minimization Techniques
Review of Boolean Algebra. De Morgan’s Theorem. Minterm and Maxtermexpressions and conversions. Reduction techniques such as K Maps and Quine-McCluskey. Glitches and how to avoid them
Synchronous State Machine Design and Analysis:
Word problem to FSM design and documentation (flow chart and bubble arrow).Mealy and Moore machines. Implementation of FSMs using Flip Flops and logicgates. Derivation of timing diagrams. Timing Diagram to FSM design anddocumentation. One-Hot coding of FSMs.Use of logic analyser
Microprocessor external device access
Address decoding - full and aliased. Transaction handshake techniques. Bus interfacing between different sized microprocessor and external device buses.
Electrical Characteristics I:
Setup, hold, propagation delay, Critical Path - Maximum frequency of digitalcircuits. Input and Output Timing calculations. Effect of clock skew on circuitswith examples.Metastability and MTBF equations. Design of two flip-flop synchronizer andmetastability calculations.
Electrical Characteristics II:
Transmission line model and effects. Signal propagation, reflection, undershoot,overshoot, crosstalk, ground bounce and how to minimise them. Terminationschemes. Probes and how to use them. Reliability of digital circuits subject toelectrical overstress.Logic level definitions for different families. Correct values for pull-up/pulldownresistors. Fan out and fan in calculations. Wired logic. Tri-state gates.
Asynchronous Interfacing.
Matastability and its cause by asynchronous inputs to FSMs. Correct use and analysis of double synchroniser. Use of grey coding of FSMs in this context.
Schematic Analysis
Analysis of circuit diagrams back to representational diagrams.
| Module Content & Assessment | |
|---|---|
| Assessment Breakdown | % |
| Other Assessment(s) | 30 |
| Formal Examination | 70 |